Novena iCE40 Add-On


The Novena laptop from Studio Kousagi features a large, fast, and extremely flexible Xilinx Spartan 6 FPGA which allows all sorts of interesting devices to be connected, from an oscilloscope to a flash ROM emulator for hacking SD cards. However, building projects for the Xilinx FPGA requires the use of a piece of software from Xilinx called ISE, which has two significant problems for Novena users:-

  1. It’s not open source.
  2. It doesn’t actually run on the Novena!

Unfortunately, there’s no open source software currently able to build a Xilinx bitstream, and it’s not possible to run ISE on anything except an x86 machine. However, there are other FPGAs which do have suitable open source build tools available; in particular, Clifford Wolf’s IceStorm project provides a suitable toolchain for the Lattice iCE40 family of FPGAs. These are small and relatively slow FPGAs, but are straightforward to work with, and IceStorm’s toolchain runs quickly and without complications on Novena.

This wouldn’t be much use without an iCE40 connected to the Novena in some way, however, and so I’ve designed a board which does exactly that. The iCE40 add-on for the Novena provides an iCE40HX4K connected to the FPGA port on the Novena, and an identical FPGA connector for your I/O devices. For example, you can sandwich the iCE40 board between the Novena and the General-Purpose Breakout Board which all Novenas ship with. This gives you a way to work on FPGA-based projects on the Novena itself, and to do so without needing either the use of an x86 machine nor closed source software.

Novena with iCE40 Add-On and GPBB conected

Making the Board

The board is designed to be produced cheaply and is small enough (50mm x 50mm) to fit within the lowest price brackets of most PCB manufacturers (although it’s a 4-layer design). The bill of materials cost should be around $20, with the PCB itself available at $30 for 10 from

If you’re interested in making these boards, the sources are available under the Apache 2.0 license

The board is designed with mounting holes in the appropriate places to stack with the main Novena board using generic 5mm stand-offs, and for the GPBB or any other add-ons to attach in the same way on top. The top-side connector is rotated 90 degrees relative to the first, such that the GPBB or similar will stick out above the Novena SSD port. This is simply because there isn’t room with the normal orientation, because the screen hinge is in the way (although it also simplifies the routing).

The iCE40HX4K and FX10 connectors used on the board have quite tight pin-pitch, and assembly is somewhat fiddly if you’re not used to these component packages. I found the easiest way to solder these down properly was to simply drag a blob of solder along the whole row of pins and then wick off the excess with some solder braid. Normal drag soldering works poorly, as the board is quite a good conductor of heat and as a result the solder doesn’t flow well between pins.


The board is designed to provide a similar interface to that provided by the Spartan 6 to any Novena accessory . As such, all pins on the pass-through header are wired to the FPGA. Unfortunately, this doesn’t leave enough spare iCE40 pins to fully wire the Novena connector. The entire SPI interface of the iCE40 is connected to the Xilinx on the Novena, and this is how your code can be uploaded to the iCE40. A full mapping of all of the pins between the Xilinx and iCE40, and iCE40 and GPBB, is available for download below.

I’ve written a suitable program to feed a bitstream into the iCE40 by bit-banging through the Xilinx, and this allows you to upload a full iCE40 bitstream in under a second. The Xilinx part needs a bitstream which provides a suitable basic GPIO interface, of course, and both the loader program and a suitable Xilinx bitstream are available here.

The example project above will perform a simple binary count using the LEDs on the GPBB.

To compile and build the example:-

  1. Install IceStorm, yosys, and arachene-pnr from Project IceStorm.
  2. Install the GPBB example project code from
  3. Build the iCE40 loader program (just run “make”)
  4. Configure the Xilinx FPGA using the bitstream above and the configuration script in bunnie’s GPBB example archive. (./ ~/Downloads/novena_fpga.bit)
  5. Run “make” in the iCE40 example project directory to build the iCE40 bitstream.
  6. Run ice40-loader with the newly generated bitstream (example.bin) as a parameter to program the iCE40. (ice40-loader example.bin)

To make full use of the iCE40, a bus bridge will be required to allow the iMX6 on the Novena to communicate with the iCE40, and to allow the iCE40 to make use of the DDR RAM connected to the Xilinx part.  I haven’t yet written this, but the work’s underway, and I’ll update this page when it’s complete.