I’ve now got the iCE40 add-on board for the novena up and running. There are a couple of defects on the board design that need corrected before you can get one of these boards to run. These are:
Missing power to the VCC_SPI pin (pin 72, top pin on the right-hand side of the chip, nearest the 1.2V regulator) – this just needs jumpered to any available 3.3V point. Since it’s the very corner pin, there’s no difficulty connecting this by hand.
Bad footprint for the pass-through connector – the FX10A_80P_8 connector footprint I’ve used is too narrow, and it makes it very difficult to solder by hand. Reflow should be OK as long as the solder resist layer isn’t excessively thick on your boards – the pads are in the right place, just too short.
I’ll do a revision of the board layout when I get some time, but for now, this is pretty functional.
I’ve written a basic loader for the iCE40 , which uses a slightly modified GPBB Xilinx bitstream for now. I hope to write a proper bus bridge for the Xilinx to interface between the two ICs, but for now it’s enough to get blinkenlights working. The sources (and a copy of the compiled Xilinx bitstream) are available here.
I’ve also included a basic blinkenlights demo for the GPBB when piggy-backed on the iCE40.
I’ve been working on an add-on board for the Novena open-source laptop, which provides an iCE40HX4K FPGA on a mezzanine board designed to fit in between the Novena and any add-on boards.
The reason this is useful is that Clifford Wolf’sicestorm project provides a fully open-source FPGA toolchain for the iCE40 that can run locally on the Novena, thereby removing the need for an x86 desktop machine when playing with FPGA projects. The Xilinx FPGA will act as a bus bridge between the iCE40 and the Novena, and (hopefully) provide access to RAM too, using a fixed, shared, FPGA design.
The board is intended to sit in the same location as the normal GPBB board would in a Novena laptop, and to provide a rotated FPGA header for the GPBB or other add-on boards to connect to, positioned such that it will sit above the SSD. This isn’t ideal, but the Novena layout is very tight for space around the FPGA connector, so it’s the best way I could fit in space for a whole second board.
At this point, I’ve drawn up a PCB design for the board, and I’ve ordered the first batch from dirtypcbs.com to try out. If anyone’s curious to look at the schematics or board, they’re available here in DipTrace format. Everything’s under the Apache 2.0 license, to match the Novena itself.
I recently found, in an old box of random electronics, a pocket dictionary of the 12-in-one spellchecker variety. The board had two large chip-on-board ICs on it, both covered with the usual black epoxy of doom. The actual traces routing between the two were relatively sparse, and I was somewhat curious what the architecture of the device actually was, so I decided I’d like to de-encapsulate the chips to see what was making it tick.
I’ve heard many times in the past that the best way to do this is by careful application of fuming nitric acid. Unfortunately, that’s somewhat controlled in the UK as it’s considered a precursor for making explosives; as a result, I didn’t have any to hand. However, I thought it might be interesting to try a different approach – a laser cutter.
I have a generic 40W chinese laser cutter, of the kind you can pick up cheaply on eBay. This particular laser has been upgraded very slightly with some better stepper control electronics and an air assist nozzle for the head; however, it’s still using all the original optics and laser. The air assist is the only relevant improvement for this job.
I set the PCB with the COB blob up under the laser, and fed in a simple half-inch square bitmap to the laser control software to be engraved. This made the laser perform a raster pattern across the surface of the COB device, neatly etching away the epoxy. If you’re trying this yourself, I used three passes, with the laser at full power and set to 300mm/sec and air assist on.
A single pass yielded a noticable depth of cut into the epoxy blob, with a fairly good surface; it was a little dusty (the various unpleasant byproducts of burning epoxy tend to recondense on nearby surfaces), but the laser was clearly cutting the epoxy fine. The question was whether it would trash the silicon underneath.
After the third pass, the die surface started to become visible, and so I stopped and cleaned off the surface with a brush. Unfortunately, I was a little heavy-handed with the brush, and some of the gold bond wires were broken as I did – they were actually intact before. However, I managed to get a pretty good view of the chip surface, and a look at the layout. Apologies for the poor photograph quality – I was using a biological microscope not intended for top illumination, and it has bad flare problems with the reflections from the IC surface.
From this, I think it’s pretty clear that this chip is just a ROM of some sort, and any clever behaviour is implemented on the other chip on the board, Unfortunately I managed to shatter that chip while trying a different process for removing it from the epoxy blob of doom, so I have no photographs of that to show.
I hope this helps if anyone else needs urgently to deencapsulate a chip and work out what’s inside it; it’s faster (less than 5 minutes on the laser) and simpler than the nitric acid approach, and while it doesn’t yield a perfect result, it’s good enough for basic identification. Most importantly, the laser doesn’t seem to cut any of the metal on the chip, nor the bond wires, nor the silicon itself, despite chewing rapidly through the black epoxy.